This appendix contains information on individual hardware products. The information consists of ROM locations, switch settings, and so on. The sections are organized by manufacturer and product. Table B-1 summarizes the specific boards described in this appendix.
The directory $PSS_ROOT/bsps/idt79381 contains a pSOSystem BSP for the IDT 79S381 Evaluation Board.
Install the four ROMs labeled U55, U56, U57 and U58 in the appropriate sockets. The pSOSystem ROMs for the IDT 79S381 are 27010 EPROMs. Jumper W5 should be set to position A-B, which is the default, to match the size of the EPROMs. All other jumpers and DIP-switches should be kept in their default positions.
A terminal should be connected to the DB-25 connector marked TERMINAL (J2). The serial protocol is 9600 baud, 8-bit data, 1 stop bit, and no parity.
The pSOSystem BSP for the IDT 79S381 supports both serial channels on the target board. The pSOSystem serial channel number 1 corresponds to the port labeled "TERMINAL" on the IDT 79S381, while channel number 2 corresponds to the port named "AUX" on the target board.
For the purpose of using the tutorials in this manual, on-board RAM begins at address 0x80000000. The Boot ROMs use RAM from 0x80000800 through 0x8005FFFF. The entry point for downloaded systems is0x80060000.
The IDT 79S381 is available with varying DRAM sizes. The sizes range from 2 Mb through 16 Mb. In the memory map diagram below, x should be changed to reflect the amount of DRAM present on the board.
The boot ROM for the IDT 79S381 is built using the code in sample application apps/tftp. You can build a boot ROM by following these steps:
The shell variable $PSS_ROOT should contain the absolute pathname of your pSOSystem directory (/xx/yy/pSOSystem/MIPS). The shell variable $PATH must include the directory $PSS_ROOT/bin/sparc.
The initialized data is located beginning at 0x80000800 in RAM. The Boot ROM code will copy it there at startup, but the S-records must be relocated so that the initialized data will be placed into the Boot ROM immediately behind the code segment. This will be done automatically during ROM build when a call is made to the $PSS_ROOT/bin/sparc/sr2bin command. The output will be the relocated S-record file rom.hex and a binary file rom.bin.
Note: Make sure that the tools smove and exbin are located in the directory $PSS_ROOT/bin/sparc. Otherwise edit the shell script sr2bin and change the following lines:
SMOVE=$PSS_ROOT/bin/sparc/smove
EXBIN=$PSS_ROOT/bin/sparc/exbin
To split the rom.hex file for programming, use the $PSS_ROOT/bin/sparc/splitrom command as shown below:
$PSS_ROOT/bin/sparc/splitrom rom.hex b bfc00000 128 \
rom.1 rom.2 rom.3 rom.4
The resulting files rom.1 through rom.4 should be programmed into ROMs to be put in sockets U55 through U58 respectively.
For the IDT 79S381 pSOSystem Boot ROMs, the Ethernet hardware address is a configuration parameter. This parameter should be set according to the Ethernet hardware address assigned to the board. The documentation that comes with the board should include the assigned address.
The directory PSS_ROOT/bsps/idt79460 contains a pSOSystem BSP for the IDT 79S460 Evaluation Board.
Install the Boot ROM in the U6 socket. The pSOSystem ROM for the IDT 79S460 is a 27C040 EPROM. All jumpers and DIP-switches should be kept in their default positions.
A terminal should be connected to the DB-9 connector named Chan 1. The serial protocol is 9600 baud, 8-bit data, 1 stop bit, and no parity.
The pSOSystem BSP for the IDT 79S460 supports both serial channels on the target board. The pSOSystem serial channel number 1 corresponds to the port named Chan 1 on the IDT 79S460, while channel number 2 corresponds to the port named Chan 2 on the target board.
For the purpose of using the tutorials in this manual, on-board RAM begins at address 0x80000000. The Boot ROMs use RAM from 0x80000800 through 0x8005FFFF. The entry point for downloaded systems is 0x80060000.
The IDT 79S460 is available with varying DRAM sizes. The sizes range from 2 Mb through 96 Mb. In the memory map diagram below, xy should be changed to reflect the amount of DRAM present on the board.
B.1.5 Setting the Ethernet Hardware Address
B.2 IDT 79S460 Evaluation Board
B.2.1 ROM Installation and Hardware Setup
B.2.2 Serial Channel Usage
B.2.3 Memory Layout
The Boot ROM for the IDT 79S460 is built using the code in sample application apps/tftp. You can build a Boot ROM by following these steps:
The shell variable $PSS_ROOT should contain the absolute pathname of your pSOSystem directory (/xx/yy/pSOSystem/MIPS). The shell variable $PATH must include the directory $PSS_ROOT/bin/sparc.
The initialized data is located beginning at 0x80000800 in RAM. The Boot ROM code will copy it there at startup, but the S-records must be relocated so that the initialized data will be placed into the Boot ROM immediately behind the code segment. This will be done automatically during the ROM build when a call is made to the $PSS_ROOT/bin/sparc/sr2bin command. The output will be the relocated S-record file rom.hex and a binary file rom.bin.
Note: Make sure that the tools smove and exbin are located in the directory $PSS_ROOT/bin/sparc. Otherwise edit the shell script sr2bin and change the following lines:
SMOVE=$PSS_ROOT/bin/sparc/smove
EXBIN=$PSS_ROOT/bin/sparc/exbin
To split the rom.hex file for programming, use the $PSS_ROOT/bin/sparc/splitrom command as shown below:
$PSS_ROOT/bin/sparc/splitrom rom.hex b 9fc00000 512\ rom.1
The resulting file rom.1 should be programmed into the ROM to be put in socket U6.
For the IDT 79S3460 pSOSystem Boot ROMs, the Ethernet hardware address is a configuration parameter. This parameter should be set according to the Ethernet hardware address assigned to the board. The documentation that comes with the board should include the assigned address.
The directory PSS_ROOT/bsps/idt79465 contains a pSOSystem BSP for the IDT 79S465 Evaluation Board.
Install the four flash ROMs labeled U51, U52, U53, and U54 in the appropriate sockets. The pSOSystem ROMs for the IDT 79S465 board are 29F040 flash PROMs. All jumpers and DIP-switches should be kept in their default positions.
A terminal should be connected to the DB-25 connector marked J16. The serial protocol is 9600 baud, 8-bit data, 1 stop bit and no parity.
The pSOSystem BSP for the IDT 79S465 supports both serial channels on the target board. The pSOSystem serial channel number 1 corresponds to the port marked J16 on the IDT 79S465, while channel number 2 corresponds to the port marked J17 on the target board.
The IDT 79S465 board has both SRAM and DRAM. For the purpose of using the tutorials in this manual, on-board SRAM begins at address 0x80000000 and on-board DRAM begins at address 0x80400000. The Boot ROMs use RAM from 0x80400000 through 0x8045FFFF, so do not attempt to use them to download code to this area. The entry point for the downloaded system is 0x80460000.
The IDT 79S465 board is available with varying DRAM sizes. In the memory map diagram below, xy should be changed to reflect the amount of DRAM present on the board.
B.2.5 Setting the Ethernet Hardware Address
B.3 IDT 79S465 Evaluation Board
B.3.1 ROM Installation and Hardware Setup
B.3.2 Serial Channel Usage
B.3.3 Memory Layout
The Boot ROM for the IDT 79S465 is built using the code in sample application apps/tftp. You can build a Boot ROM by following these steps:
The shell variable $PSS_ROOT should contain the absolute pathname of your pSOSystem directory (/xx/yy/pSOSystem/MIPS). The shell variable $PATH must include the directory $PSS_ROOT/bin/sparc.
The initialized data is located beginning at 0x80400000 in RAM. The Boot ROM code will copy it there at startup, but the S-records must be relocated so that the initialized data will be placed into the Boot ROM immediately behind the code segment. This will be done automatically during the ROM build when a call is made to the $PSS_ROOT/bin/sparc/sr2bin command. The output will be the relocated S-record file rom.hex and a binary file rom.bin.
Note: Make sure that the tools smove and exbin are located in the directory $PSS_ROOT/bin/sparc. Otherwise edit the shell script sr2bin and change the following lines:
SMOVE=$PSS_ROOT/bin/sparc/smove
EXBIN=$PSS_ROOT/bin/sparc/exbin
To split the rom.hex file for programming, use the $PSS_ROOT/bin/sparc/splitrom command as shown below:
$PSS_ROOT/bin/sparc/splitrom rom.hex b bfc00000 512 \
rom.1 rom.2 rom.3 rom.4
The resulting files rom.1 through rom.4 should be programmed into the ROMs.
For the IDT 79S3465 pSOSystem Boot ROMs, the Ethernet hardware address is a configuration parameter. This parameter should be set according to the Ethernet hardware address assigned to the board. The documentation that comes with the board should include the assigned address.
The directory PSS_ROOT/bsps/dve3900 contains a pSOSystem BSP for the Densan DVE-R3900 Board.
Install the Boot ROMs in the PROM sockets marked HIGH and LOW. The pSOSystem ROM for the DVE-R3900 board is two 29C4096 EPROMs. All jumpers and DIP-switches should be kept in their default positions.
A terminal should be connected to the DB-9 connector marked J2 on the front panel. The serial protocol is 9600 baud, 8-bit data, 1 stop bit and no parity.
The pSOSystem BSP for the DVE-R3900 supports both serial channels on the target board. The pSOSystem serial channel number 1 corresponds to the port connector marked J2 on the DVE-R3900, while channel number 2 corresponds to the port connector marked J3 on the target board.
For the purpose of using the tutorials in this manual, on-board RAM begins at address 0x80000000. The Boot ROMs use RAM from 0x80000800 through 0x8005FFFF. The entry point for downloaded systems is 0x80060000.
The DVE-R3900 comes with 16MB of RAM. The memory map is given below.
B.3.5 Setting the Ethernet Hardware Address
B.4 Densan DVE R3900 Board
B.4.1 ROM Installation and Hardware Setup
B.4.2 Serial Channel Usage
B.4.3 Memory Layout
The Boot ROM for the DVE-R3900 is built using the code in sample application apps/tftp. You can build a Boot ROM by following these steps:
The shell variable $PSS_ROOT should contain the absolute pathname of your pSOSystem directory (/xx/yy/pSOSystem/MIPS). The shell variable $PATH must include the directory $PSS_ROOT/bin/sparc.
The initialized data is located beginning at 0x80000800 in RAM. The Boot ROM code will copy it there at startup, but the S-records must be relocated so that the initialized data will be placed into the Boot ROM immediately behind the code segment. This will be done automatically during the ROM build when a call is made to the $PSS_ROOT/bin/sparc/sr2bin command. The result of the ROM build is the relocated S-record file rom.hex and a binary file rom.bin.
Note: Make sure that the tools smove and exbin are located in the directory $PSS_ROOT/bin/sparc. Otherwise edit the shell script sr2bin and change the following lines:
SMOVE=$PSS_ROOT/bin/sparc/smove
EXBIN=$PSS_ROOT/bin/sparc/exbin
To split the rom.hex file for programming, use the $PSS_ROOT/bin/sparc/splitrom command as shown below:
$PSS_ROOT/bin/sparc/splitrom rom.hex ws bfc00000 \
512 rom.1 rom.2
The resulting files rom.1 and rom.2 should be programmed into ROMs to be put in the HIGH and LOW sockets respectively.
For the DVE-R3900 pSOSystem Boot ROMs, the Ethernet hardware address is a configuration parameter. Normally the Densan DVE-R3900 boards are shipped with unique Ethernet hardware addresses stored in the BBRAM. If not, a unique value needs to be assigned to the Ethernet hardware address by the system administrator.
The directory PSS_ROOT/bsps/lsi4001 contains a pSOSystem BSP for the LSI MR4001 board.
Install the Boot Flash ROMs in the corresponding Flash sockets marked on Flash ROM labels. The pSOSystem Flash ROMs for the LSI MR4001 board are four 29C010 Flash ROMs. All jumpers and DIP-switches should be kept in their default positions.
A terminal should be connected to the DB-9 connector marked U28 on the board. The serial protocol is 9600 baud, 8-bit data, 1 stop bit and no parity.
The pSOSystem BSP for the LSI MR4001 supports both serial channels on the target board. The pSOSystem serial channel number 1 corresponds to the port connector marked U28 on the LSI MR4001, while channel number 2 corresponds to the port connector marked U43 on the target board.
For the purpose of using the tutorials in this manual, on-board DRAM begins at address 0x81000000. The Boot ROMs use RAM from 0x81000000 through 0x8105FFFF. The entry point for the downloaded system is 0x81060000.
The LSI MR4001 board is available with either 4MB or 8MB of DRAM and 1MB of SRAM. In the memory map given below, "X" should be changed to reflect the amount of DRAM present on the board.
B.4.5 Setting the Ethernet Hardware Address
B.5 LSI 4001 Board
B.5.1 ROM Installation and Hardware Setup
B.5.2 Serial Channel Usage
B.5.3 Memory Layout
The Boot ROM for the LSI MR4001 is built using the code in sample application apps/tftp. You can build a Boot ROM by following these steps:
The shell variable $PSS_ROOT should contain the absolute pathname of your pSOSystem directory (/xx/yy/pSOSystem/MIPS). The shell variable $PATH must include the directory $PSS_ROOT/bin/sparc.
The initialized data is located beginning at 0x81000000 in RAM. The Boot ROM code will copy it there at startup, but the S-records must be relocated so that the initialized data will be placed into the Boot ROM immediately behind the code segment. This will be done automatically during the ROM build when a call is made to the $PSS_ROOT/bin/sparc/sr2bin command.
The result of the ROM build is the relocated S-record file rom.hex and a binary file rom.bin.
Note: Make sure that the tools smove and exbin are located in the directory $PSS_ROOT/bin/sparc. Otherwise edit the shell script sr2bin and change the following lines:
SMOVE=$PSS_ROOT/bin/sparc/smove
EXBIN=$PSS_ROOT/bin/sparc/exbin
To split the rom.hex file for programming, use the $PSS_ROOT/bin/sparc/splitrom command as shown below:
$PSS_ROOT/bin/sparc/splitrom rom.hex b bfc00000 128 \
rom.1 rom.2 rom.3 rom.4
The resulting files rom.1, rom.2, rom.3, and rom.4 should be programmed into the four Flash ROMs.
For the LSI MR4001 pSOSystem Boot ROMs, the Ethernet hardware address is a configuration parameter. This parameter should be set according to the Ethernet hardware address assigned to the board. The documentation that comes with the board should include the assigned address.
The directory PSS_ROOT/bsps/lsi100 contains a pSOSystem BSP for the LSI Integra 100 Board.
Install the Boot Flash ROMs in the corresponding Flash sockets marked on Flash ROM labels. The pSOSystem Flash ROMs for the Integra 100 board are four 29C010 Flash ROMs. All jumpers and DIP-switches should be kept in their default positions.
A terminal should be connected to the RS232 connector marked CON11 on the board. The serial protocol is 9600 baud, 8-bit data, 1 stop bit and no parity.
The pSOSystem BSP for the LSI Integra 100 supports both serial channels on the target board. The pSOSystem serial channel number 1 corresponds to the RS232 connector marked CON11 on the Integra 100, while channel number 2 corresponds to the RS232 connector marked CON12 on the target board.
For the purpose of using the tutorials in this manual, on-board DRAM begins at address 0x80000000. The Boot ROMs use RAM from 0x81000000 through 0x8105FFFF. The entry point for downloaded systems is 0x81060000.
The LSI Integra 100 board is available with 3MB DRAM. The memory map is given below.
B.5.5 Setting the Ethernet Hardware Address
B.6 LSI Integra100 Board
B.6.1 ROM Installation and Hardware Setup
B.6.2 Serial Channel Usage
B.6.3 Memory Layout
The Boot ROM for the LSI Integra 100 is built using the code in sample application apps/proberom. You can build a Boot ROM by following these steps:
The shell variable $PSS_ROOT should contain the absolute pathname of your pSOSystem directory (/xx/yy/pSOSystem/MIPS). The shell variable $PATH must include the directory $PSS_ROOT/bin/sparc.
The initialized data is located beginning at 0x81000000 in RAM. The Boot ROM code will copy it there at startup, but the S-records must be relocated so that the initialized data will be placed into the Boot ROM immediately behind the code segment. This will be done automatically during the ROM build when a call is made to the $PSS_ROOT/bin/sparc/sr2bin command.
The result of the ROM build is the relocated S-record file rom.hex and a binary file rom.bin.
Note: Make sure that the tools smove and exbin are located in the directory $PSS_ROOT/bin/sparc. Otherwise edit the shell script sr2bin and change the following lines:
SMOVE=$PSS_ROOT/bin/sparc/smove
EXBIN=$PSS_ROOT/bin/sparc/exbin
To split the rom.hex file for programming, use the $PSS_ROOT/bin/sparc/splitrom command as shown below:
$PSS_ROOT/bin/sparc/splitrom rom.hex b bfc00000 128 \
rom.1 rom.2 rom.3 rom.4
The resulting files rom.1, rom.2, rom.3 and rom.4 should be programmed into the four Flash ROMs.
For the Integra 100 pSOSystem Boot ROMs, the Ethernet hardware address is a configuration parameter. This parameter should be set according to the Ethernet hardware address assigned to the board. The documentation that comes with the board should include the assigned address.
B.6.5 Setting the Ethernet Hardware Address